The present invention relates to a test circuit arrangement. The present invention can be applied to the detection of write/read errors in SRAM devices (SRAM, S-random access memories). The present invention in particular relates to latch units consisting of N-type transistors and P-type transistors, e.g. NMOS and PMOS transistors or NPN and PNP bipolar transistors.
Latch units are used in various circuit arrangements. For example, the core of a SRAM cell comprises latch units in order to store the desired information. In order to guarantee the functionality of latch units it is essential to perform reliable tests that can be used in an efficient manner.